Formal Synthesis for Pipeline Design?
نویسندگان
چکیده
Holger Hinrichsen, Hans Eveking, and Gerd Ritter Dept. of Electrical and Computer Engineering Darmstadt University of Technology, D-64283 Darmstadt, Germany hinrichsen/eveking/[email protected] Abstract. A method of formally correct synthesis is presented and applied to the automatic construction of pipelined processors. The approach is based on a small set of correctness-preserving transformations that are e ciently cross-checked by an independent formal veri cation tool. Basic pipeline strategies as well as automatic post-synthesis veri cation are provided.
منابع مشابه
Automatic Pipeline Synthesis and Formal Verification from Transactional Datapath Specifications
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